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fn8696 rev.4.00 oct 17, 2017 isl68201 single-phase r4 digital hybrid p wm controller with pmbus/smbus/ i 2 c and pfm datasheet fn8696 rev.4.00 page 1 of 32 oct 17, 2017 the isl68201 is a single-phase, synchronous buck pwm controller featuring intersil?s proprietary r4? technology. it supports a wide 4.5v to 24v input voltage range and a wide 0.5v to 5.5v output range. inte grated ldos provide controller bias voltage, allowing for single supply operation. the isl68201 includes a pmbus/smbus/i 2 c interface for device configuration and telemetry (v in , v out , i out , and temperature) and fault reporting. intersil?s proprietary r4 control scheme has extremely fast transient performance, accurately regulated frequency control and all internal compensation. an efficiency enhancing pfm mode can be enabled to greatly improve light-load efficiency. the isl68201?s serial bus allows for easy r4 loop optimization, resulting in fast transient performance over a wide range of applications, including all ceramic output filters. the isl68201 has four 8-bit conf iguration pins, which provide very flexible configuration options (frequency, v out , r4 gain, etc.) without the need for built- in nvm memory. this results in a design flow that closely matches traditional analog controllers, while still offering the design flexibility and feature set of a digital pmbus/smbus/i 2 c interface. the isl68201 also features remote voltage se nsing and completely eliminates any potential difference between remote and local grounds. this improves regulation and protection accuracy. a precision enable input is available to coordinate the start-up of the isl68201 with other voltage rails, especially useful for power sequencing. applications ? high efficiency and high density pol digital power ?fpga, asic, and memory supplies ? data center: servers, storage systems ? wired infrastructure: routers, switches, and optical networking ? wireless infrastruc ture: base station related literature ? isl68201 product page features ? intersil?s proprietary r4 technology - linear control loop for optimal transient response - variable frequency and duty cycle control during load transient for fastest possible response - inherent voltage feed-forward for wide range input ? input voltage range: 4.5v to 24v ? output voltage range: 0.5v to 5.5v ? 0.5% dac accuracy with remote sense ? support all ceramic solutions ? integrated ldos for single input rail solution ? smbus/pmbus/i 2 c compatible, up to 1.25mhz ? 256 boot-up voltage levels with a configuration pin ? eight switching frequency options from 300khz to 1.5mhz ? pfm operation option, compatible with isl99140 for improved light-load efficiency ? start-up into precharged load ? precision enable input to set higher input uvlo and power sequence as well as fault reset ? power-good monitor for soft-start and fault detection ? comprehensive fault protection for high system reliability - over-temperature protection - output overcurrent and short-circuit protection - output overvoltage and undervoltage protection - open remote sense protection ? compatible with 5v or 3.3v pwm input drmos or smart power stage (sps) ? compatible with intersil?s powernavigator software table 1. single-phase r4 digital hybrid pwm controller options part number integrated driver pwm output pmbus/smbus/i 2 c interface compatible devices isl68200 yes no yes discrete mosfets or dual channel mosfets isl68201 no yes yes intersil power stages: isl99140, isl99227, isl99125b, isl99135b intersil drivers: isl6596, isl6609, isl6627, isl6622, isl6208
isl68201 fn8696 rev.4.00 page 2 of 32 oct 17, 2017 table of contents typical applications circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ic supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 resistor reader (patented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 boot-up voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 thermal monitoring and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 i out calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pgood monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 pfm mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 smbus, pmbus, and i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 r4 modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 general application design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 output filter design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 design and layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 voltage regulator design materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
isl68201 fn8696 rev.4.00 page 3 of 32 oct 17, 2017 typical applications circuits figure 1. wide range input and output applications figure 2. 5v input application vsen rgnd csen csrtn gnd scl sda pgood en pgood en vcc pvcc vin lgin phase ntc i 2 c/ smbus/ pmbus 4.75 to 24v 0.5v to 5.5v iout prog1-4 salert vcc 7vldo vcc ntc 4.7f 1.0f 1.0f 0.1f 1.54k 10k ncp18xh103j03rb beta = 3380 4 boot pwm isl99140 ug lg pwm 100 fccm vcc v out < 7vldo 1.7v \ vsen rgnd csen csrtn gnd scl sda pgood en pgood en vcc pvcc vin lgin phase ntc i 2 c/ smbus/ pmbus 4.5 to 5.5v 0.5v to 2.5v iout prog1-4 salert vcc 7vldo vcc ntc 4.7f 1.0f 1.0f 0.1f 1.54k 10k ncp18xh103j03rb beta = 3380 4 boot pwm isl99140 ug lg pwm 100 fccm vcc v out < 7vldo 1.7v \
fn8696 rev.4.00 page 4 of 32 oct 17, 2017 isl68201 block diagram fccm pwm fccm lgin pvcc pwm gnd overvoltage/ soft-start r4 modulator reference voltage circuitry por vin csrtn prog1 prog2 prog3 rgnd pgood vsen vcc en internal compensation amplifier + switching frequency undervoltage prog4 csen current sense overcurrent (ocp) and gnd and fault logic ntc and temperature compensation scl sda salert 7v ldo smbus/pmbus/i 2 c interface 7vldo 5v ldo vin 7vldo pvcc iout over-temperature (otp) iout temp vout vin ocp otp driver pwm and pfm control driver pgood circuitry - figure 3. isl68201 simplified functional block diagram
isl68201 fn8696 rev.4.00 page 5 of 32 oct 17, 2017 pin configuration isl68201 (24 ld 4x4 qfn) top view ordering information part number ( notes 1 , 2 , 3 ) part marking temp range (c) package (rohs compliant) pkg. dwg. # isl68201irz isl 68201i -40 to +85 24 ld 4x4 qfn l24.4x4c ISL68201-99125DEMO1Z 16a demo board with on-board transient isl68201-99135demo1z 20a demo board with on-board transient isl68201-99140demo1z 35a demo board with on-board transient notes: 1. add ?-t? suffix for 6k unit, ?-t7a? suffix for 250 unit or ?-tk? for 1k unit for tape and reel options. refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), see the product information page for isl68201 . for more information on msl, see tb363 . lgin pvcc pwm gnd fccm gnd sda pgood rgnd vsen csrtn csen en vin 7vldo vcc scl salert prog1 prog2 prog3 prog4 iout ntc 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 gnd (pad) functional pin descriptions pin number symbol description 1 en precision enable input. pulling en above the rising threshol d voltage initiates the soft-sta rt sequence, while pulling en be low the failing threshold voltage suspends th e voltage regulator (vr) operation. 2 vin input voltage pin for r4 loop and ldos (5v and 7v). place a high quality low esr ceramic capacitor (1.0 f, x7r) in close proximity to the pin. external se ries resistor is not advised. 3 7vldo 7v ldo from vin is used to bias current sensing am plifier. place a high quality low esr ceramic capacitor (1.0 f, x7r, 10v+) in close proximity to the pin. 4 vcc logic bias supply that should be connected to pvcc rail externally. place a high quality low esr ceramic capacitor (1 f, x7r) from this pin to gnd. 5 scl synchronous clock signal input of smbus/pmbus/i 2 c. 6 salert output pin for transferring the active low signal driv en asynchronously from the vr controller to smbus/pmbus. 7 sda i/o pin for transferring data signals between smbus/pmbus/i 2 c host and vr controller. 8 pgood power-good open-drain indicator output. 9 rgnd this pin monitors the negative rail of regulator output. connect to ground at point of regulation.
isl68201 fn8696 rev.4.00 page 6 of 32 oct 17, 2017 10 vsen this pin monitors the positive rail of re gulator output. connect to point of regulation. 11 csrtn this pin monitors the negative flow of output current with a series resistor and for overcurrent protection and telemetr y. the series resistor sets the current gain and should be within 40 ? and 3.5k . 12 csen this pin monitors the positive flow of output current for overcurrent protection and telemetry. 13 ntc input pin for the temperature measurement. connect this pin through an ntc thermistor (10k , ? ~ 3380) and a decoupling capacitor (~0.1 f) to gnd and a resistor (1.54k ) ? to vcc of the controller. the voltage at this pin is inversely proportional to the vr temperature. 14 iout output current monitor pin. an external resistor sets the gain and an external capacitor provides the averaging function; an external pull-up resistor to vcc is recomm ended to calibrate the no load offset. see ? i out calibration ? on page 19 . 15 prog4 programming pin for modulator (r4) rr impedance and output slew rate during soft-start (ss) and dynamic vid (dvid). it also sets av gain multiplier to 1x or 2x and determines the av gain on prog3. 16 prog3 programming pin for ultrasonic pfm operation, fault behavior, switching frequency, and r4 (av) control loop gain. 17 prog2 programming pin for pwm/pfm mode, temperature compensation, and serial bus (smbus/pmbus/i 2 c) address. 18 prog1 programming pin for boot-up voltage. 19, 21 gnd ground pin, connect directly to system ground plane. 20 fccm output signal low to work with drmos isl99140 fo r diode emulation in pfm mode; signal high for pwm mode. 22 pwm pwm output and is compatible with 3.3v or 5v pw m input external driver, drmos, or smart power stage. 23 pvcc output of the 5v ldo and input for the lgate and ugate mosfet driver circuits. place a high quality low esr ceramic capacitors (4.7 f or higher, x7r) in close proximity to the pin. 24 lgin low-side gate signal input to complete the internal fll loop. a 100 series impedance from low-side gate drive signal to this pin is required. pad gnd return of logic bias supply vcc. connect directly to system ground plane with at least four vias. functional pin descriptions (continued) pin number symbol description
isl68201 fn8696 rev.4.00 page 7 of 32 oct 17, 2017 absolute maximum rating s thermal information vcc, pvcc, vsen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v input voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27v 7vldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to gnd, 7.75v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to gnd, vcc + 0.3v esd rating human body model (tested per js-001-2010) . . . . . . . . . . . . . . . . .2.5kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . 200v charge device model (tested per js-002-2014) . . . . . . . . . . . . . . . . 1kv latch-up (tested per jesd78d, class 2, level a) . . . . 100ma at +125c thermal resistance (typical) ? ja (c/w) ? jc (c/w) 24 ld qfn ( notes 4 , 5 ) . . . . . . . . . . . . . . . . 39 2.5 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c wide range input voltage, v in , figure 1 . . . . . . . . . . . . . . . . . 4.75v to 24v 5v application input voltage, v in , v cc , pvcc, figure 2 . . . . . . 4.5v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high-effective thermal conductivity test board with ?direct attach? fe atures. see tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications all typical specifications t a = +25c, v cc = 5v. boldface limits apply across th e operating temperature range, -40c to +85c, unless otherwise stated. parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit vcc and pvcc vcc input bias current i vcc en = 5v, v cc = 5v, f sw = 500khz, dac = 1v 14 16.5 ma en = 0v, v cc = 5v 14 16.5 ma pvcc input bias current i pvcc en = 5v, v cc = 5v, f sw = 500khz, dac = 1v 2 ma en = 0v, v cc = 5v 1.0 ma vcc and vin por threshold vcc, pvcc rising por threshold voltage 4.2 4.35 v vcc, pvcc falling por threshold voltage 3.80 3.95 4.15 v v in , 7vldo rising por threshold voltage 4.2 4.35 v v in , 7vldo falling por threshold voltage 3.80 3.95 4.15 v enable input en high threshold voltage v enthr 0.81 0.84 0.87 v en low threshold voltage v enthf 0.71 0.76 0.81 v dac accuracy dac accuracy (t a = 0c to +85c) 2.5v < dac 5.5v -0.5 0.5 % 1.6v < dac 2.5v -0.75 0.75 % 1.2v < dac 1.6v -10 10 mv 0.5v dac 1.2v -8 8 mv dac accuracy (t a = -45c to +85c) 2.5v < dac 5.5v -0.75 0.75 % 1.6v < dac 2.5v -1.0 1.0 % 1.2v < dac 1.6v -11 11 mv 0.5v dac 1.2v -9 9 mv channel frequency 300khz configuration pwm mode 260 300 335 khz 400khz configuration pwm mode 345 400 450 khz
isl68201 fn8696 rev.4.00 page 8 of 32 oct 17, 2017 500khz configuration pwm mode 435 500 562 khz 600khz configuration pwm mode 510 600 670 khz 700khz configuration pwm mode 610 700 790 khz 850khz configuration pwm mode 730 850 950 khz 1000khz configuration pwm mode 865 1000 1120 khz 1500khz configuration pwm mode 1320 1500 1660 khz soft-start and dynamic vid soft-start and dvid slew rate 0.0616 0.078 0.096 mv/s 0.13 0.157 0.18 mv/s 0.25 0.315 0.37 mv/s 0.53 0.625 0.70 mv/s 1.05 1.25 1.40 mv/s 2.10 2.50 2.80 mv/s 4.20 5.00 5.60 mv/s 8.60 10.0 10.9 mv/s soft-start delay from enable high excluding 5.5ms por timeout. see figures 21 and 22 140 200 260 s remote sense bias current of vsen and rgnd pins 250 a maximum differential input voltage 6.0 v power-good pgood pull-down impedance r pg pgood = 5ma sink 10 50 pgood leakage current i pg pgood = 5v 1.0 a ldos 5v ldo regulation v in = 12v, load = 50ma 4.85 5.00 5.15 v 5v dropout v in = 4.75v, load = 50ma 4.45 v 5v ldo current capability 125 ma 7v ldo regulation 250a load 7.2 7.4 7.5 v 7v dropout v in = 4.75v, 250a load 4.50 v 7v ldo current capability not recommended for external use 2 ma current sense average ocp trip level i oc_trip 82 100 123 a short-circuit protection threshold 130 % i ocp sensed current tolerance 74 78 83 a sensed current tolerance 35 38 42 a maximum common-mode input voltage 7vldo = 7.4v 5.7 v vcc = pvcc = 7vldo = 4.5v 2.8 v electrical specifications all typical specifications t a = +25c, v cc = 5v. boldface limits apply across th e operating temperature range, -40c to +85c, unless otherwise stated. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl68201 fn8696 rev.4.00 page 9 of 32 oct 17, 2017 fault protection uvp threshold voltage latch 68 74 80 % dac start-up ovp threshold voltage 0v v boot 1.08v 1.10 1.15 1.25 v 1.08v < v boot 1.55v 1.58 1.65 1.75 v 1.55v < v boot 1.85v 1.88 1.95 2.05 v 1.85v < v boot 2.08v 2.09 2.15 2.25 v 2.08v < v boot 2.53v 2.56 2.65 2.75 v 2.53v < v boot 3.33v 3.36 3.45 3.6 v 3.33v < v boot 5.5v 5.52 5.65 5.85 v start-up ovp hysteresis 100 mv ovp rising threshold voltage v ovrth 0.5 dac 5.5 114 120 127 % dac ovp falling threshold voltage v ovfth 0.5 dac 5.5 96 100 108 % dac over-temperature shutdown threshold read_temp = 72h 20 22.31 26 % vcc over-temperature shutdown reset threshold read_temp = 8eh 25 27.79 30 % vcc smbus/pmbus/i 2 c signal input low voltage 1 v signal input high voltage 1.6 v signal output low voltage 4ma pull-up current 0.4 v date, alert # pull-down impedance 11 50 clock maximum speed 1.25 mhz clock minimum speed 0.05 mhz telemetry update rate 108 s timeout 25 30 35 ms pmbus accessible timeout from all rails? por see figure 21 5.5 6.5 ms note: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. electrical specifications all typical specifications t a = +25c, v cc = 5v. boldface limits apply across th e operating temperature range, -40c to +85c, unless otherwise stated. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl68201 fn8696 rev.4.00 page 10 of 32 oct 17, 2017 operation the following sections provide a detailed description of the isl68201 operation. ic supplies the isl68201 has four bias pins: vin, 7vldo, pvcc, and vcc. the pvcc and 7vldo voltage rails are 5v ldo and 7.4v ldo supplied by vin, respectively, while the vcc pin needs to connect to the pvcc rail externally to be biased. for 5v input applications, all these pins should be tied toge ther and biased by a 5v supply. because the vin pin voltage information is used by the r4 modulator loop, the user cannot bi as vin with a series resistor. in addition, the vin pin cannot be biased independently from other rails. enable and disable the ic is disabled until the 7vldo, pvcc, vcc, vin, and en pins increase above their respective ri sing threshold voltages and the typical 5.5ms timeout (worst case = 6.5ms) expires, as shown in figures 21 and 22 on page 22 . the controller will become disabled when the 7vldo, pvcc, vcc, vin, or en pins drop below their respective falling por threshold voltages. the precision threshold en pin allows the user to set a precision input uvlo level with an external resistor divider, as shown in figure 4 . for 5v input applications or wide range input applications, the en pin can direct ly connect to vcc, as shown in figure 5 . if an external enable control signal is available and is an open-drain signal, a pull-up impedance (100k or higher) can be used. in addition, based on the on_o ff_config [02h] setting, the ic can be enabled or disabled by the serial bus command ?operation [01h]? and/or en pin. see table 11 on page 25 for more details. resistor reader (patented) the isl68201 offers four programming pins to customize their regulator specifications. the detail s of these pins are summarized in table 2 , followed by the detailed desc ription of resistor reader operation. intersil has developed a high resolution adc using a patented technique with a simple 1%, 100ppm/k or better temperature coefficient resistor divider. th e same type of resistors are preferred so that it has similar change over temperature. in addition, the divider is compared to the internal divider off v cc and gnd nodes and therefore must refer to vcc and gnd pins, not through any rc decoupling network. figure 4. input uvp configuration external circuit isl68201 100k 9.09k vin soft- en start vin uvlo = 10.08v/9.12v figure 5. 5v input or wide range input configuration external circuit isl68201 vcc soft- en start r en is needed only if the user wants to r en control the ic with an external enable signal optional vin uvlo = 4.20/3.95v figure 6. simplified resistor divider adc external circuit isl68201 r up r dw vcc adc register table
isl68201 fn8696 rev.4.00 page 11 of 32 oct 17, 2017 the r up and r dw values for a particular parameter set can be found using the power navigator gui. data for corresponding registers can be read out usin g the serial pmbus command (dc to df). note : the case of 10k r up or r dw is the same as 0k r up or r dw . table 3. prog 1 resistor reader example prog1 (dc) r up (k ) r dw (k ) v out (v) 00h open 0 0.797 20h open 21.5 0.852 40h open 34.8 0.898 60h open 52.3 0.953 80h open 75 1.000 a0h open 105 1.047 c0h open 147 1.102 e0h open 499 1.203 1fh 0 open 1.352 3fh 21.5 open 1.500 5fh 34.8 open 1.797 7fh 52.3 open 2.500 9fh 75 open 3.000 bfh 105 open 3.297 dfh 147 open 5.000 ffh 499 open 0.000 table 4. prog 2 resistor reader example prog2 (dd) r up (k ) r dw (k )pwm/pfm temp comp pm_addr (7-bit) 00h open 0 enabled 30 60h 20h open 21.5 enabled 15 60h 40h open 34.8 enabled 5 60h 60h open 52.3 enabled off 60h 80h open 75 disabled 30 60h a0h open 105 disabled 15 60h c0h open 147 disabled 5 60h e0h open 499 disabled off 60h 1fh 0 open enabled 30 7f 3fh 21.5 open enabled 15 7f 5fh 34.8 open enabled 5 7f 7fh 52.3 open enabled off 7f 9fh 75 open disabled 30 7f bfh 105 open disabled 15 7f dfh 147 open disabled 5 7f ffh 499 open disabled off 7f table 5. prog 3 resist or reader example prog3 (de) r up (k ) r dw (k ) ultrasonic pfm fault behavior f sw (khz) r4 gain 1x 2x 00h open 0 disabled retry 300 42 84 20h open 21.5 disabled retry 700 42 84 40h open 34.8 disabled latch 300 42 84 60h open 52.3 disabled latch 700 42 84 80h open 75 enabled retry 300 42 84 a0h open 105 enabled retry 700 42 84 c0h open 147 enabled latch 300 42 84 e0h open 499 enabled latch 700 42 84 1fh 0 open disabled retry 600 1 2 3fh 21.5 open disabled retry 1500 1 2 5fh 34.8 open disabled latch 600 1 2 7fh 52.3 open disabled latch 1500 1 2 9fh 75 open enabled retry 600 1 2 bfh 105 open enabled retry 1500 1 2 dfh 147 open enabled latch 600 1 2 ffh 499 open enabled latch 1500 1 2 table 6. prog 4 resist or reader example prog4 (df r up (k ) r dw (k ) ss rate (mv/s) rr (k ?? avmlti 00h open 0 1.25 200 1x 20h open 21.5 2.5 200 1x 40h open 34.8 5 200 1x 60h open 52.3 10 200 1x 80h open 75 0.078 200 1x a0h open 105 0.157 200 1x c0h open 147 0.315 200 1x e0h open 499 0.625 200 1x 1fh 0 open 1.25 800 2x 3fh 21.5 open 2.5 800 2x 5fh 34.8 open 5 800 2x 7fh 52.3 open 10 800 2x 9fh 75 open 0.078 800 2x bfh 105 open 0.157 800 2x dfh 147 open 0.315 800 2x ffh 499 open 0.625 800 2x
isl68201 fn8696 rev.4.00 page 12 of 32 oct 17, 2017 soft-start the isl68201-based regulator has four periods during soft-start, as shown in figure 7 on page 12 . after a 5.5ms timeout (worst case = 6.5ms) of bias supplies, as shown in figures 21 and 22 on page 22 , when the en pin reaches ab ove its enable threshold, the controller begins the first soft-start ramp after a fixed soft-start delay period t d1 . the output voltage reaches the boot-up voltage (v boot ) at a fixed slew rate in period t d2 . then, the controller will regulate the output voltage at v boot for another period t d3 until smbus/pmbus/ i 2 c sends a new v out command. if the v out command is valid, the isl68201 will initiate the ramp until the voltage reaches the new vout_command voltage in period t d4 . the soft-start time is the sum of the four periods, as shown in equation 1 . t d1 is a fixed delay with the typical value as 200s. t d3 is determined by the time to obtain a new valid vout_command voltage from smbus/pmbus/i 2 c bus. if the vout_command is valid before the output reaches th e boot-up voltage, the output will turn around to respond to the new vout_command code. during t d2 and t d4 , the isl68201 digitally controls the dac voltage change. the ramp time t d2 and t d4 can be calculated based on equations 2 and 3 , after the slew rate is set by the prog4 pin. the isl68201 supports precharged start-up, which initiates the first pwm pulse until the internal reference (dac) reaches the precharged level at ramp_rate, programmed by prog4 or d5[2:0]. when the precharged level is below v boot , the output walks up to the v boot at ramp_rate and releases pgood at t d1 + t d2 . when the precharged output is above v boot but below ovp, it walks down to v boot at ramp_rate and then releases pgood at t d1 + t d2 , in which t d2 is defined in equation 4 and longer than a normal start-up. the isl68201 supports precharged load start-up to the maximum v out of 5.5v with sufficient boot capacitor charge. for an extended precharged load, the boot capacitor will be discharged to ?pvcc - v out -v d ? by the high-side drive circuits? standby current. for instance, an extended 4v precharged load, the boot capacitor will reduce to a less-than-1v boot capacitor voltage, which is insufficient to power up the vr; in this case, it is recommended to let the output drop below 2.5v with an external bleed resistor before issuing another soft-start command. boot-up voltage programming an 8-bit pin prog1 is dedicated for the boot-up voltage programmability, which offers 256 options 0v and 0.5v to 5.5v, as in table 7 . the most popular boot-up voltage levels are placed on the tie-low spots (0h, 20h, 40h, 60h, 80h, a0h, c0h, e0h) and the tie-high spots (1fh, 3fh, 5fh, 7fh, 9fh, bfh, dfh, ffh) for easy programming, as summarized in table 3 . 0v boot-up voltage is considered as ?off,? th e driver will be in tri-state and the internal dac will set to 0v. in addition, if the vout_command (21h) is executed successfully 5.5ms (typically, worst 6.5ms) after vcc por and before enable, it will override the boot-up voltage set by the prog1 pin. t ss t d1 t d2 t d3 t d4 +++ = (eq. 1) figure 7. soft-start waveforms en t d3 t d4 pgood t d1 t d2 0v v out pre-charged< v boot v boot v boot < pre-charged < ovp t d2 v boot ramp_rate -------------------------------------- ? s ?? = (eq. 2) t d4 v out v boot C ramp_rate ----------------------------------------- - ? s ?? = (eq. 3) table 7. prog1 8-bit (boot-up voltage) binary code hex code v boot (v) vout command code (hex) delta from previous code (mv) 00000000 0 0.7969 66 00000001 1 0.5000 40 00000010 2 0.5078 41 7.8125 00000011 3 0.5156 42 7.8125 00000100 4 0.5234 43 7.8125 00000101 5 0.5313 44 7.8125 00000110 6 0.5391 45 7.8125 00000111 7 0.5469 46 7.8125 00001000 8 0.5547 47 7.8125 00001001 9 0.5625 48 7.8125 00001010 a 0.5703 49 7.8125 00001011 b 0.5781 4a 7.8125 00001100 c 0.5859 4b 7.8125 00001101 d 0.5938 4c 7.8125 00001110 e 0.6016 4d 7.8125 00001111 f 0.6094 4e 7.8125 00010000 10 0.6172 4f 7.8125 00010001 11 0.6250 50 7.8125 00010010 12 0.6328 51 7.8125 00010011 13 0.6406 52 7.8125 00010100 14 0.6484 53 7.8125 t d2 v precharged ramp_rate -------------------------------------------- v precharged v boot C ramp_rate --------------------------------------------------------------- ------- - ? s ?? + = (eq. 4)
isl68201 fn8696 rev.4.00 page 13 of 32 oct 17, 2017 00010101 15 0.6563 54 7.8125 00010110 16 0.6641 55 7.8125 00010111 17 0.6719 56 7.8125 00011000 18 0.6797 57 7.8125 00011001 19 0.6875 58 7.8125 00011010 1a 0.6953 59 7.8125 00011011 1b 0.7031 5a 7.8125 00011100 1c 0.7109 5b 7.8125 00011101 1d 0.7188 5c 7.8125 00011110 1e 0.7266 5d 7.8125 00011111 1f 1.3516 ad 00100000 20 0.8516 6d 00100001 21 0.7344 5e 7.8125 00100010 22 0.7422 5f 7.8125 00100011 23 0.7500 60 7.8125 00100100 24 0.7578 61 7.8125 00100101 25 0.7656 62 7.8125 00100110 26 0.7734 63 7.8125 00100111 27 0.7813 64 7.8125 00101000 28 0.7891 65 7.8125 00101001 29 0.7969 66 7.8125 00101010 2a 0.8047 67 7.8125 00101011 2b 0.8125 68 7.8125 00101100 2c 0.8203 69 7.8125 00101101 2d 0.8281 6a 7.8125 00101110 2e 0.8359 6b 7.8125 00101111 2f 0.8438 6c 7.8125 00110000 30 0.8516 6d 7.8125 00110001 31 0.8594 6e 7.8125 00110010 32 0.8672 6f 7.8125 00110011 33 0.8750 70 7.8125 00110100 34 0.8828 71 7.8125 00110101 35 0.8906 72 7.8125 00110110 36 0.8984 73 7.8125 00110111 37 0.9063 74 7.8125 00111000 38 0.9141 75 7.8125 00111001 39 0.9219 76 7.8125 00111010 3a 0.9297 77 7.8125 00111011 3b 0.9375 78 7.8125 table 7. prog1 8-bit (boot-up voltage) (continued) binary code hex code v boot (v) vout command code (hex) delta from previous code (mv) 00111100 3c 0.9453 79 7.8125 00111101 3d 0.9531 7a 7.8125 00111110 3e 0.9609 7b 7.8125 00111111 3f 1.5000 c0 01000000 40 0.8984 73 01000001 41 0.9688 7c 7.8125 01000010 42 0.9766 7d 7.8125 01000011 43 0.9844 7e 7.8125 01000100 44 0.9922 7f 7.8125 01000101 45 1.0000 80 7.8125 01000110 46 1.0078 81 7.8125 01000111 47 1.0156 82 7.8125 01001000 48 1.0234 83 7.8125 01001001 49 1.0313 84 7.8125 01001010 4a 1.0391 85 7.8125 01001011 4b 1.0469 86 7.8125 01001100 4c 1.0547 87 7.8125 01001101 4d 1.0625 88 7.8125 01001110 4e 1.0703 89 7.8125 01001111 4f 1.0781 8a 7.8125 01010000 50 1.0859 8b 7.8125 01010001 51 1.0938 8c 7.8125 01010010 52 1.1016 8d 7.8125 01010011 53 1.1094 8e 7.8125 01010100 54 1.1172 8f 7.8125 01010101 55 1.1250 90 7.8125 01010110 56 1.1328 91 7.8125 01010111 57 1.1406 92 7.8125 01011000 58 1.1484 93 7.8125 01011001 59 1.1563 94 7.8125 01011010 5a 1.1641 95 7.8125 01011011 5b 1.1719 96 7.8125 01011100 5c 1.1797 97 7.8125 01011101 5d 1.1875 98 7.8125 01011110 5e 1.1953 99 7.8125 01011111 5f 1.7969 e6 01100000 60 0.9531 7a 01100001 61 1.2031 9a 7.8125 01100010 62 1.2109 9b 7.8125 table 7. prog1 8-bit (boot-up voltage) (continued) binary code hex code v boot (v) vout command code (hex) delta from previous code (mv)
isl68201 fn8696 rev.4.00 page 14 of 32 oct 17, 2017 01100011 63 1.2188 9c 7.8125 01100100 64 1.2266 9d 7.8125 01100101 65 1.2344 9e 7.8125 01100110 66 1.2422 9f 7.8125 01100111 67 1.2500 a0 7.8125 01101000 68 1.2578 a1 7.8125 01101001 69 1.2656 a2 7.8125 01101010 6a 1.2734 a3 7.8125 01101011 6b 1.2813 a4 7.8125 01101100 6c 1.2891 a5 7.8125 01101101 6d 1.2969 a6 7.8125 01101110 6e 1.3047 a7 7.8125 01101111 6f 1.3125 a8 7.8125 01110000 70 1.3203 a9 7.8125 01110001 71 1.3281 aa 7.8125 01110010 72 1.3359 ab 7.8125 01110011 73 1.3438 ac 7.8125 01110100 74 1.3516 ad 7.8125 01110101 75 1.3594 ae 7.8125 01110110 76 1.3672 af 7.8125 01110111 77 1.3750 b0 7.8125 01111000 78 1.3828 b1 7.8125 01111001 79 1.3906 b2 7.8125 01111010 7a 1.3984 b3 7.8125 01111011 7b 1.4063 b4 7.8125 01111100 7c 1.4141 b5 7.8125 01111101 7d 1.4219 b6 7.8125 01111110 7e 1.4297 b7 7.8125 01111111 7f 2.5000 140 10000000 80 1.0000 80 10000001 81 1.4375 b8 7.8125 10000010 82 1.4453 b9 7.8125 10000011 83 1.4531 ba 7.8125 10000100 84 1.4609 bb 7.8125 10000101 85 1.4688 bc 7.8125 10000110 86 1.4766 bd 7.8125 10000111 87 1.4844 be 7.8125 10001000 88 1.4922 bf 7.8125 10001001 89 1.5000 c0 7.8125 table 7. prog1 8-bit (boot-up voltage) (continued) binary code hex code v boot (v) vout command code (hex) delta from previous code (mv) 10001010 8a 1.5078 c1 7.8125 10001011 8b 1.5156 c2 7.8125 10001100 8c 1.5234 c3 7.8125 10001101 8d 1.5313 c4 7.8125 10001110 8e 1.5391 c5 7.8125 10001111 8f 1.5469 c6 7.8125 10010000 90 1.5547 c7 7.8125 10010001 91 1.5625 c8 7.8125 10010010 92 1.5703 c9 7.8125 10010011 93 1.5781 ca 7.8125 10010100 94 1.5859 cb 7.8125 10010101 95 1.5938 cc 7.8125 10010110 96 1.6016 cd 7.8125 10010111 97 1.6094 ce 7.8125 10011000 98 1.6172 cf 7.8125 10011001 99 1.6250 d0 7.8125 10011010 9a 1.6328 d1 7.8125 10011011 9b 1.6406 d2 7.8125 10011100 9c 1.6484 d3 7.8125 10011101 9d 1.6563 d4 7.8125 10011110 9e 1.6641 d5 7.8125 10011111 9f 3.0000 180 10100000 a0 1.0469 86 10100001 a1 1.6719 d6 7.8125 10100010 a2 1.6797 d7 7.8125 10100011 a3 1.6875 d8 7.8125 10100100 a4 1.6953 d9 7.8125 10100101 a5 1.7031 da 7.8125 10100110 a6 1.7109 db 7.8125 10100111 a7 1.7188 dc 7.8125 10101000 a8 1.7266 dd 7.8125 10101001 a9 1.7344 de 7.8125 10101010 aa 1.7422 df 7.8125 10101011 ab 1.7500 e0 7.8125 10101100 ac 1.7578 e1 7.8125 10101101 ad 1.7656 e2 7.8125 10101110 ae 1.7734 e3 7.8125 10101111 af 1.7813 e4 7.8125 10110000 b0 1.7891 e5 7.8125 table 7. prog1 8-bit (boot-up voltage) (continued) binary code hex code v boot (v) vout command code (hex) delta from previous code (mv)
isl68201 fn8696 rev.4.00 page 15 of 32 oct 17, 2017 10110001 b1 1.7969 e6 7.8125 10110010 b2 1.8047 e7 7.8125 10110011 b3 1.8125 e8 7.8125 10110100 b4 1.8203 e9 7.8125 10110101 b5 1.8281 ea 7.8125 10110110 b6 1.8359 eb 7.8125 10110111 b7 1.9141 f5 78.125 10111000 b8 1.9922 ff 78.125 10111001 b9 2.0703 109 78.125 10111010 ba 2.1484 113 78.125 10111011 bb 2.2266 11d 78.125 10111100 bc 2.3047 127 78.125 10111101 bd 2.3828 131 78.125 10111110 be 2.4609 13b 78.125 10111111 bf 3.2969 1a6 11000000 c0 1.1016 8d 11000001 c1 2.4688 13c 7.8125 11000010 c2 2.4766 13d 7.8125 11000011 c3 2.4844 13e 7.8125 11000100 c4 2.4922 13f 7.8125 11000101 c5 2.5000 140 7.8125 11000110 c6 2.5078 141 7.8125 11000111 c7 2.5156 142 7.8125 11001000 c8 2.5234 143 7.8125 11001001 c9 2.6016 14d 78.125 11001010 ca 2.6797 157 78.125 11001011 cb 2.7578 161 78.125 11001100 cc 2.8359 16b 78.125 11001101 cd 2.9141 175 78.125 11001110 ce 2.9922 17f 78.125 11001111 cf 3.0703 189 78.125 11010000 d0 3.1484 193 78.125 11010001 d1 3.2266 19d 78.125 11010010 d2 3.2813 1a4 54.6875 11010011 d3 3.2891 1a5 7.8125 11010100 d4 3.2969 1a6 7.8125 11010101 d5 3.3047 1a7 7.8125 11010110 d6 3.3125 1a8 7.8125 11010111 d7 3.3203 1a9 7.8125 table 7. prog1 8-bit (boot-up voltage) (continued) binary code hex code v boot (v) vout command code (hex) delta from previous code (mv) 11011000 d8 3.3281 1aa 7.8125 11011001 d9 3.4063 1b4 78.125 11011010 da 3.4844 1be 78.125 11011011 db 3.5625 1c8 78.125 11011100 dc 3.6406 1d2 78.125 11011101 dd 3.7188 1dc 78.125 11011110 de 3.7969 1e6 78.125 11011111 df 5.0000 280 11100000 e0 1.2031 9a 11100001 e1 3.8750 1f0 78.125 11100010 e2 3.9531 1fa 78.125 11100011 e3 4.0313 204 78.125 11100100 e4 4.1094 20e 78.125 11100101 e5 4.1875 218 78.125 11100110 e6 4.2656 222 78.125 11100111 e7 4.3438 22c 78.125 11101000 e8 4.4219 236 78.125 11101001 e9 4.5000 240 78.125 11101010 ea 4.5781 24a 78.125 11101011 eb 4.6563 254 78.125 11101100 ec 4.7344 25e 78.125 11101101 ed 4.8125 268 78.125 11101110 ee 4.8906 272 78.125 11101111 ef 4.9688 27c 78.125 11110000 f0 4.9766 27d 7.8125 11110001 f1 4.9844 27e 7.8125 11110010 f2 4.9922 27f 7.8125 11110011 f3 5.0000 280 7.8125 11110100 f4 5.0078 281 7.8125 11110101 f5 5.0156 282 7.8125 11110110 f6 5.0234 283 7.8125 11110111 f7 5.0313 284 7.8125 11111000 f8 5.1094 28e 78.125 11111001 f9 5.1875 298 78.125 11111010 fa 5.2656 2a2 78.125 11111011 fb 5.3438 2ac 78.125 11111100 fc 5.4219 2b6 78.125 11111101 fd 5.4922 2bf 70.3125 11111110 fe 5.5000 2c0 7.8125 table 7. prog1 8-bit (boot-up voltage) (continued) binary code hex code v boot (v) vout command code (hex) delta from previous code (mv)
isl68201 fn8696 rev.4.00 page 16 of 32 oct 17, 2017 as shown in table 7 , 1 step is 2 -7 = 7.8125mv; some selections are higher than 1 step from adjacent codes. however, the resolution is 7.8125mv around the popular voltage regulation points, as in table 3 on page 11 , for fine-tuning purposes. for finer than 7.8125mv tuning, a larg e ratio resistor divider can be placed on the vsen pin between the output (v out ) and rgnd for positive offset or v cc for negative offset, as shown in figure 8 . current sensing the isl68201 supports inductor dcr sensing, or resistive sensing techniques, and senses current continuously for fast response. the current sense amplifier uses the csen and csrtn inputs to reproduce a signal proportional to the inductor current, i l . the sense current, i sen , is proportional to the inductor current and is used for current reporting and overcurrent protection. the input bias current of the curr ent sensing amplifier is typically 10s of na. less than 15k input impedance co nnected to csen pin is preferred to minimize the offset error, that is, use a larger c value (select 0.22f to 1f instead of 0.1f when needed). in addition, the current sensing gain resistor connected to csrtn pin should be within 40 ? to 3.5k . inductor dcr sensing an inductor?s winding is characteri stic of a distributed resistance, as measured by the direct current resistance (dcr) parameter. a simple r-c network across the inductor extracts the dcr voltage, as shown in figure 9 . the voltage on the capacitor v c , can be shown to be proportional to the inductor current i l , as in equation 5 . if the r-c network components are selected so that the r-c time constant (= r*c) matches the in ductor time constant (= l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr. with the internal low-offset current amplifier, the capacitor voltage v c is replicated across the sense resistor r isen . therefore, the current out of the csrtn pin, i sen , is proportional to the inductor current. equation 6 shows that the ratio of the inductor current to the sensed current, i sen , is driven by the value of the sense resistor and the dcr of the inductor. the inductor dcr value will increase as the temperature increases. therefore, the sensed current will increase as the temperature of the current sense element increases. to compensate for the temperature effect on the sensed current signal, the integrated temperat ure compensation function of isl68201 should be used. the integrated temperature compensation function is described in ? thermal monitoring and compensation ? on page 18 . resistive sensing for accurate current sense, a dedicated current-sense resistor, r sense , in series with each output inductor, can serve as the current sense element (see figure 10 ). this technique, however, reduces overall converter efficiency due to the additional power loss on the current sense element r sense . 11111111 ff 0 0 table 7. prog1 8-bit (boot-up voltage) (continued) binary code hex code v boot (v) vout command code (hex) delta from previous code (mv) figure 8. external programmable regulation - + vsen v cc v out - + vsen v out a. v out higher than dac b. v out lower than dac rgnd v c s ?? s l dcr ------------- ? 1 + ?? ?? dcr i l ? ?? ? src 1 + ? ?? --------------------------------------------------------------- ----- - = (eq. 5) i sen i l dcr r isen ----------------- - ? = (eq. 6) figure 9. dcr sensing configuration i out i sen i l dcr r isen ------------------- = - + csen current sense v in csrtn r isen dcr l inductor r v out c out - + v c (s) c i l s ?? - + v l isl68201 internal circuit driver place these in close proximity to isl68201 optional
isl68201 fn8696 rev.4.00 page 17 of 32 oct 17, 2017 a current sensing resistor has a distributed parasitic inductance, known as equivalent series inductance (esl) parameter, typically less than 1nh. a simple r-c ne twork across the current-sense resistor extracts the r sen voltage, as shown in figure 10 on page 17 . the voltage on the capacitor v c , can be shown to be proportional to the inductor current i l , see equation 7 . if the r-c network components are selected so that the rc time constant matches the esl-r sen time constant (r*c = esl/r sen ), the voltage across the capacitor v c is equal to the voltage drop across the r sen , that is, proportional to the inductor current. as an example, a typical 1m sense resistor can use r = 348 and c = 820pf for the matching. figures 11 and 12 show the sensed waveforms without and with matching rc when using resistive sense. equation 8 shows that the ratio of the inductor current to the sensed current, i sen , is driven by the value of the sense resistor and the r isen . l/dcr or esl/r sen matching figure 13 shows the expected load transient response waveforms if l/dcr or esl/r sen is matching the r-c time constant. when the load current has a square change, the iout pin voltage (v iout ) without a decoupling capacitor also has a square response. however, there is always some pcb contact impedance of current sensing components between the two current sensing points; it hardly accounts into the l/dcr or esl/r sen matching calculation. fine tuning the matching is done in the board level to improve overall transient performance and system reliability. if the r-c timing constant is too large or too small, v c (s) will not accurately represent real-time output current and will worsen the overcurrent fault response. figure 14 shows the iout pin transient voltage response when the r-c timing constant is too small. v iout will sag excessively upon load insertion and may create a system failure or early overcurrent trip. figure 15 shows the transient response when the r-c timing constant is too large. v iout is sluggish in reaching its final value. the excessive delay on current sensing will not provide a fast ocp response and hurt system reliability. note that the integrated thermal compensation applies to the dc current, but not the ac current; therefore, the peak current seen by the controller will increase as the temperature decreases and can potentially trigger an ocp event. to overcome this issue, the rc should be over-matching l/ dcr at room temperature by (-40c +25c)*0.385%/c = +25% for -40c operation. figure 10. sense resistor in series with inductors i out i sen i l r sen r isen ----------------- - = - + csen current sense csrtn r isen r sen l v out c out i l isl68201 r - + v c (s) c esl r sense - + v r internal circuit place these in close proximity to isl68201 optional v c s ?? s esl r sen --------------- - ? 1 + ?? ?? r sen i l ? ?? ? src 1 + ? ?? --------------------------------------------------------------- ---------- = (eq. 7) figure 11. voltage across r without rc figure 12. voltage across c with matching rc i sen i l r sen r isen ----------------- - ? = (eq. 8) figure 13. desired load tr ansient response waveforms load v iout figure 14. load transient response when r-c time constant is too small load v iout figure 15. load transient response when r-c time constant is too large load v iout
isl68201 fn8696 rev.4.00 page 18 of 32 oct 17, 2017 thermal monitoring and compensation the diagram of thermal monitoring function block is shown in figure 16 on page 18 . one ntc resistor should be placed close to the respective power stage of the voltage regulator vr to sense the operational temperature, and pull-up resistors are needed to form the voltage dividers for the ntc pin. as the temperature of the power stage increases, the resi stance of the ntc will reduce, resulting in the reduced voltage at the ntc pin. figure 18 on page 18 shows the tm voltage over the temperature for a typical design with a recommended 10k ntc (p/n: ncp15xh103j03rc from murata, ? = 3380) and 1.54k resistor rtm. it is recommended to use those resistors for accurate temperature compensation because the internal thermal digital code is developed based on these two components. if a different value is used, the temperature coefficient must be close to 3380 and rtm must be scaled accordingly. for instance, if ntc = 20k ( ? = 3380), then rtm should be 20k /10k *1.54k =3.08k . the isl68201 supports inductor dcr sensing, or resistive sensing techniques. the inductor dcr has a positive temperature coefficient, which is about +0.385%/c. because the voltage across the inductor is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor dcr. to obtain the correct current information, the isl68201 uses the voltage at the ntc pin and ?tcomp? register to compensate the temperature impact on the sensed current. the block diagram of this function is shown in figure 17 . when the ntc is placed close to the current sense component (inductor), the temperature of th e ntc will track the temperature of the current sense component. therefore, the ntc pin voltage can be used to obtain the temperature of the current sense component. because the ntc could pick up noise from phase node, a 0.1f ceramic decoupling capacitor is recommended on the ntc pin in close proximity to the controller. based on the v cc voltage, the isl68201 converts the ntc pin voltage to a digital signal for temperature compensation. with the nonlinear a/d converter of the isl68201, the ntc digital signal is linearly proportional to the ntc temperature. for accurate temperature compensation , the ratio of the ntc voltage to the ntc temperature of the practical design should be similar to that in figure 18 . figure 16. block diagram of thermal monitoring and protection vcc oc r tm ntc - + r ntc thermal trip +136c/+122oc otp isl68201 beta~ 3380 c r tm r ntc ntc tcomp non-linear a /d a /d figure 17. block diagram of integrated temperature compensation figure 18. the ratio of tm voltage to ntc temperature with recommended part 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 temperature (c) v tm /v cc (%)
isl68201 fn8696 rev.4.00 page 19 of 32 oct 17, 2017 because the ntc attaches to the pcb, but not directly to the current sensing component, it in herits high thermal impedance between the ntc and the current sensing element. the ?tcomp? register values can be used to correct the temperature difference between ntc and the current sense component. as shown in figure 19 , the ntc should be placed in proximity to the output rail; do not place it close to the mosfet side, which generates much more heat. the isl68201 multiplexes the ?tcomp? value with the ntc digital signal to obtain the adjustment gain to compensate the temperature impact on the se nsed channel current. the compensated current signal is used for i out and overcurrent protection functions. the tcomp ?o ff? code is to disable thermal compensation when the current sensing element is the resistor or smart power stage (internally thermal compensated) that has little thermal drifting. the thermal compensation design procedure for inductor current sensing is summarized as follows: 1. properly choose the voltage divider for the ntc pin to match the ntc voltage vs temperature curve with the recommended curve in figure 18 on page 18 . 2. run the actual board under the full load and the desired airflow condition. 3. after the board reaches the thermal steady state (often takes 15 minutes), record the temperature (t csc ) of the current sense component (inductor) and the voltage at ntc and vcc pins. 4. use equation 9 to calculate the resistance of the ntc, and find out the corresponding ntc temperature t ntc from the ntc datasheet or using equation 10 , where ?? is equal to 3380 for recommended ntc. 5. choose a number close to the result as in equation 11 for the ?tcomp? register. 6. run the actual board under full load again. 7. record the iout pin voltage as v1 immediately after the output voltage is stable with the full load. record the iout pin voltage as v2 after the vr reaches the thermal steady state. 8. if the iout pin voltage increases over 10mv as the temperature increases (that is, v2 - v1 > 10mv), reduce the ?tcomp? value. if the iout pin voltage decreases over 10mv as the temperature increases (that is, v1 - v2 > 10mv), increase the ?tcomp? value. the ?tcomp? value can be adjusted through the serial bus for easy thermal compensation optimization. i out calibration the current flowing out of the iout pin is equal to the sensed average current inside isl68201. a resistor is placed from the iout pin to gnd to generate a voltage, which is proportional to the load current and the resi stor value, as shown in equation 12 : where v iout is the voltage at the iout pin, r iout is the resistor between the iout pin and gnd, i load is the total output current of the converter, r isen is the sense resistor connected to the csrtn pin, and r x is the dc resistance of the current sense element, either the dcr of the inductor or r sense depending on the sensing method. the r iout resistor should be scaled to ensure that the voltage at the iout pin is typically 2.5v at 63.875a load current. the i out voltage is linearly digitized every 108s and stored in the read_iout register (8ch). a small capacitor can be placed between iout and gnd to reduce the noise impact and provide averaging, > 200s (typically). to deal with layout and design variation of different platforms, the isl68201 is intentionally trim med to negative at no load, thus, an offset can easily be added to calibrate the digitized i out table 8. tcomp values d1h tcomp (c) d1h tcomp (c) 0h 30 2h 5 1h 15 3h off figure 19. recommended placement of ntc vout powe r stage output inductor ntc r ntc at t ntc ?? v tm xr tm v cc v C tm ----------------------------- - = (eq. 9) t ntc ? r ntc at 25 ? c ?? r ntc at t ntc ?? -------------------------------------------- - ?? ?? ?? ? 298.15 ----------------- - + ln --------------------------------------------------------------- ----------------- - 273.15 C = (eq. 10) figure 20. iout no load offset calibration t comp t csc t ntc C = (eq. 11) (eq. 12) r iout 2.5vxr isen 63.875axr x ---------------------------------- 2.5vx r x xi ocp 100 ? a ------------------------ - ?? ?? 63.875axr x ----------------------------------------------- == = 2.5vxi ocp 63.875ax100 ? a -------------------------------------------- - 25vxi ocp 63.875a ---------------------------- - k ? = external circuit isl68201 r iout_up r iout_dw vcc digitized iout iout (8ch)
isl68201 fn8696 rev.4.00 page 20 of 32 oct 17, 2017 reading (8ch). hence, the analog vs digitized current slope is set by the equivalent impedance of r iout_up //r iout_dw = r iout (as in figure 20 ); the slope of the ideal curve should set to 1a/a with 0a offset. for a precision digital i out , follow the fine-tuned procedure below. steps 1 to 5 must be completed before step 6. 1. properly tune l/dcr or esl/r sen matching as shown on page 17 over the range of temperature operation. +25% over-matching l/dcr at room temperature is needed for -40c operation. 2. properly complete thermal compensation as shown in ? thermal monitoring and compensation ? on page 18 . 3. finalize the r isen resistor to set ocp for overall operating conditions and board variations as shown in ? overcurrent and short-circuit protection ? on page 20 . 4. collect no load i out current with sufficient prototypes and determine the mean of no load i out current. 5. the pull-up impedance on iout pin should be ?vcc/iout_no_load?. for instance, a mean of -2.5a i out at 0a load will need r iout_up = 2m . 6. start with the value below and then fine-tune the r iout_dw value until the average slope of various boards equals 1a/a. fault protection the isl68201 provides high syst em reliability with many fault protections, as summarized in table 9 . uvlo and otp faults will respond to the current state with hysteresis, while output ovp and output uvp faults are latch events, while output ocp and output short-circuit faults can be latch or retry events depending upon prog3 or d3[0] setting. all fault latch event can be reset by vcc cycling, toggling the enable pin and/or the serial bus operation command based on the on_off_config setting, while the ocp retry event has a hiccup time of 9ms and the regulator can be recovered when the fault is removed. overvoltage protection the ovp fault detection circuit triggers after the voltage between vsen+ and vsen- is above the ri sing overvoltage threshold. when an ovp fault is declared, the controller will be latched off and the pgood pin will be asserted low. the fault will remain latched and can be reset by v cc cycling or toggling en pin and/or the serial bus operation command based on the on_off_config setting . although the controller has latched off in response to an ovp fault, the lgate gate-driver output will retain the ability to toggle the low-side mosfet on and off, in response to the output voltage transversing the ovp risi ng and falling thresholds. the lgate gate driver will turn on the low-side mosfet to discharge the output voltage, protecting the load. the lgate gate driver will turn off the low-side mosfet when the sensed output voltage is lower than the falling overvoltage threshold (typically 100%). if the output voltage rises again, the lgate driver will again turn on the low-side mosfet when the outp ut voltage is above the rising overvoltage threshold (typically 120% ). by doing so, the ic protects the load when there is a consistent overvoltage condition. in addition to normal operatio n ovp, 5.5ms (typically, worst case = 6.5ms) after all rails (vcc, pvcc, 7vldo, vin) por and before the end of soft-start, the start-up ovp circuits are enabled to protect against an ovp event, while the ovp level is set higher than v boot . see electrical specifications on page 7 . undervoltage protection the uvp fault detection circuit triggers when the output voltage is below the undervoltage threshold (typically 74% of dac). when a uvp fault is declared, the controller will be latched off, forcing the lgate and ugate gate-driver outputs low, and the pgood pin will be asserted low. the fault will remain latched and can be reset by v cc cycling or toggling the en pin and/or the serial bus operation command based on the on_off_config setting. overcurrent and short-circuit protection the average overcurrent protection (ocp) is triggered when the internal current out of the iout pin goes above the fault threshold (typically 100a) with 1 28s blanking time. it also has a fast (50ns filter) secondary overcurrent protection whose threshold is +30% above average ocp. this protects inductor saturation from a short-circuit ev ent and provides a more robust table 9. fault protection summary fault description fault action input uvlo vin pin uvlo; or set by en pin with an external divider for a higher level. see figures 4 and 5 . shut down and recover when v in >uvlo bias uvlo vcc, pvcc, 7vldo uvlo shut down and recover when bias > uvlo start-up ovp higher than v boot . see electrical specifications on page 7 . latch off, reset by v cc or toggling enable (including en pin and/ or operation command based on the on_off_config setting) output ovp rising = 120%; falling = 100% output uvp 74% of v out , latch off output ocp average ocp = 100a with 128s blanking time. latch off (reset by v cc or toggling enable including en pin and/ or operation command based on the on_off_config setting), or retry every 9ms; option is programmable by prog3 or d3[0] short-circuit protection peak ocp = 130% of average ocp with 50ns filter. (eq. 13) r iout_dw r iout_up xr iout r iout_up r C iout -------------------------------------------------- - =
isl68201 fn8696 rev.4.00 page 21 of 32 oct 17, 2017 power train and system protection. when an ocp or short-circuit fault is declared, the controller will be latched off, forcing the lgate and ugate gate-driver outputs low, or retry with a hiccup time of 9ms. the fault response is programmable by prog3 or d3[0]. however, the latched off event can be reset by v cc cycling or toggling en pin and/or the serial bus operation command based on the on_off_config setting. equation 14 provides a starting point to set a preliminary ocp trip point, in which iocp is the targeted ocp trip point and di (as in equation 15 ) is the peak-to-peak inductor ripple current. to deal with layout and pcb cont act impedance variation, follow the fine-tuning procedure below for a more precise ocp. steps 1 to 3 must be completed before step 4. 1. properly tune l/dcr or esl/r sen matching as shown on page 17 over the range of temperature operation. +25% over-matching l/dcr at room temperature is needed for -40c operation. 2. properly complete thermal compensation as shown in ? thermal monitoring and compensation ? on page 18. 3. collect ocp trip points (io cp_measured) with sufficient prototypes and determine the mean for overall operating conditions and bo ard variations. 4. change r isen by iocp_targeted/iocp_measured percentage to meet the targeted ocp. note that if the inductor peak-to- peak current is higher or closer to 30%, the +30% threshold could be triggered instead of the average ocp threshold. however, the fine-tuning procedure can still be used. over-temperature protection as shown in figures 16 on page 18 , there is a comparator with hysteresis to compare the ntc pin voltage to the threshold set. when the ntc pin voltage is lower than 22.31% of the v cc voltage (typically +136c), it triggers over-temperature protection (otp) and shuts down the isl68201. when the ntc pin voltage is above 27.79% of the v cc voltage (typically +122.4c), the isl68201 will resu me normal operation. when an otp fault is declared, the controller forces the lgate and ugate gate-driver outputs low. pgood monitor the pgood pin indicates when the converter is capable of supplying regulated voltage. if ther e is a fault condition of a rail?s (vcc, pvcc, 7vldo, or vin) uv lo, output overcurrent (ocp), overvoltage (ovp), undervoltage (u vp), or over-temperature (otp), pgood is asserted low. note that the pgood pin is an undefined impedance with insufficient v cc (typically <2.5v). pfm mode operation in pfm mode, programmable by prog2 or serial bus d0[0:0], the switching frequency is dramatically reduced to minimize the switching loss and significantly im prove light-load efficiency. the isl68201 can enter and exit pfm mode seamlessly as the load changes. the pfm mode is only compatible with intersil?s isl99140 drmos with smod input by connecting to isl68201?s fccm output pin. incompatible power stages should operate in pwm mode. smbus, pmbus, and i 2 c operation the isl68201 features smbus, pmbus, and i 2 c with 32 programmable addresses through the prog2 pin, while smbus/pmbus includes an alert# line (salert) and packet error check (pec) to ensure data properly transmitted. the telemetry update rate is 108s (typically). the supported smbus/pmbus/i 2 c addresses are summarized in table 10 . the 7-bit format address does not include the last bit (write and read): 40-47h, 60-67h, and 70-7fh. smbus/pmbus/i 2 c allows users to program the registers as in table 11 , except for smbus/pmbus/i 2 c addresses, 5.5ms (typically, worst 6.5ms) after all rails (vcc, pvcc, 7vldo, and vin) above por. figures 21 and 22 show the initialization timing diagram for the serial bus with different state of en (enable) pin. for proper operation, users should follow the smbus, pmbus, and i 2 c protocol, as shown in figure 23 on page 23 . note that the stop (p) bit is not allowed before the repeated start condition when reading the contents of the register. when the device?s serial bus is not used, simply ground the device?s scl, sda, and salert pins and do not connect them to the bus. (eq. 14) r isen1 r x xi ocp 100 ? a ------------------------ - = r isen2 r x x ? i 2 ----- i ocp + ?? ?? 100 ? ax 100% 30% + ?? ------------------------------------------------------------- = r isen max (r isen1, r isen2 ? =
isl68201 fn8696 rev.4.00 page 22 of 32 oct 17, 2017 figure 21. simplified smbus/pmbus/i 2 c initialization timing diagram with enable low vin, pvcc, 7vldo, vcc enable 5ms 0.5ms vcc por timeout reader done 0ms to infinity v out write and read configuration write and read configuration write and read configuration v boot 0v 0m s to infinity pmbus command pmbus command pmbus command pmbus command pmbus communication not activated write and read configuration 200s ss delay figure 22. simplified smbus/pmbus/i 2 c initialization timing diagram with enable high v cc por timeout reader done v out write and read configuration write and read configuration v boot 0v 0ms to infinity pmbus command pmbus command pmbus command pmbus communication not activated write and read configuration 5ms 0.5ms enable 200s ss delay vin, pvcc, 7vldo, vcc
isl68201 fn8696 rev.4.00 page 23 of 32 oct 17, 2017 figure 23. smbus/pmbus/i 2 c command protocol s slave address_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a 1 p s slave address_0 1 7 + 1 command code 1 8 a 1 a pec 8 1 a 1 p optional 9 bits for smbus/pmbus 1. send byte protocol 2. write byte/word protocol s slave address_0 1 7 + 1 command code 1 8 a 1 8 a 1 8 a 1 8 a 1 n 1 p 3. read byte/word protocol rs slave address_1 1 7 + 1 example command: 03h clear faults example command: d0h enable_pfm ( one word, high data byte, and ack are not used) not used in i 2 c optional 9 bits for smbus/pmbus not used in i 2 c optional 9 bits for smbus/pmbus not used in i 2 c s: start condition a: acknowledge (0) n: not acknowledge (1) rs: repeated start condition p: stop condition pec: packet error checking r: read (1) w: write (0) 1 a not used for one byte word read not used for one byte word low data byte high data byte pec (this will clear all of the bits in status byte for the selecte d rail) acknowledge or data from slave, isl68201 s slave address_0 1 7 + 1 command code 1 8 byte count = n lowest data byte data byte 2 a 1 8 a 1 8 a 1 8 a 1 a 4. block write protocol example command: adh ic_ device_id (2 data byte) data byte n pec 1 8 a 1 8 a 1 a 1 p optional 9 bits for smbus/pmbus not used in i 2 c example command: 8b read_vout (two words, read voltage of the s elected rail). note: that all writable commands are read with one byte word protocol . stop (p) bit is not allowed be fore the repeated start condition when reading contents of a register.
isl68201 fn8696 rev.4.00 page 24 of 32 oct 17, 2017 figure 24. smbus/pmbus/i 2 c command protocol s slave address_0 1 7 + 1 command code 1 8 a 1 8 a 1 8 a 1 8 a 1 n 1 p 5 . block read protocol rs slave address_1 1 7 + 1 optional 9 bits for smbus/pmbus not used in i 2 c 1 a data byte pec 8 1 8 a 1 a 6. group command protocol - no more than one command can be sent t o the same address rs slave addr2_0 1 7 + 1 1 a s slave addr1_0 1 7 + 1 command code 1 8 low data byte high data byte pec a 1 8 a 1 8 a 1 8 a 1 a low data byte high data byte pec 8 1 8 a 1 8 a 1 a 1 p rs slave addr3_0 1 7 + 1 optional 9 bits for smbus/pmbus 1 a not used in i 2 c data byte 2 data byte n pec command code 8 1 a command code 8 1 a 8 1 a byte count = n 8 1 a lowest data byte example command: 8b read_vout (tw o words, read voltage of the s elected rail). note: that all writable commands are read with one byte word protocol . stop (p) bit is not allowed before the repeated start condition when reading contents of a register.
isl68201 fn8696 rev.4.00 page 25 of 32 oct 17, 2017 table 11. smbus, pmbus, and i 2 c supported commands command code access word length (byte) default value command name description 01h[7:0] r/w one 80h operation vr enable (depen ding upon on_off_config configuration): bit[7]: 0 = off (0-f); 1 = on (80-8fh) bit[6:4] = 0 bit[3:0] = don?t care 02h[7:0] r/w one 1fh on_off_config configure vr enabled by operation and/or en pin: bit[7:5] = 0 bit[4] = 1 bit[3] = operation command enable 0h = operation command has no control on vr 1h = operation command can turn on/off vr bit[2] = control pin enable 0h = en pin has no control on vr 1h = en pin can turn on/off vr bit[1] = 1 bit[0] = 1 bit[3:2] = 00b = 13h (always on) bit[3:2] = 01b = 17h (en controls vr) bit[3:2] = 10b = 1bh (o peration controls vr) bit[3:2] = 11b = 1fh (en and operation control vr) 03h send byte n/a clear_faults clear faults in status registers 20h[7:0] r one 19h vout_mode set host format of v out command. always linear format: n = -7 21h[2:0] r/w two prog1[7:0] vout_command set output voltage hex code = dec2hex [round(v out /2 -7 )] 24h[15:0] r/w two vboot+500mv vout_max set maximum output voltage that vr can command (dac vout_max). linear format. n = -7 hex code = dec2hex(roundup(vout_max/ 2 -7 ) 33h[15:0] r/w two prog3[5:3] frequency_switch set vr switching frequency (in linear format) support 8 options (n = 0): 12ch = 300khz; 190h = 400khz; 1f4h = 500khz 258h = 600khz; 2bch = 700khz; 352h = 850khz 3e8h = 1mhz; 5dch = 1.5mhz* * very high frequency is not recommended for very high duty cycle applications as the boot capacitor will not has enough time to be charged due to low lgate on time. 78h[8:0] r one status_byte fault reporting; bit7 = busy bit6 = off (reflect current state of operation and on_off_config registers as well as vr operation) bit5 = ovp bit4 = ocp bit3 = 0 bit2 = otp bit1 = bus communication error bit0 = none of above (output uvp, vout_comand > vout_max, or vout open sense) 88h[15:0] r two read_vin input voltage (n = - 4, max = 31.9375v) vin (v) = hex2dec(88 hex data - e000h) * 0.0625v 8bh[15:0] r two read_vout vr output voltage, resolution = 7.8125mv = 2 -7 vout (v) = hex2dec(8b hex data) * 2 -7 8ch[15:0] r two read_iout vr output cu rrent (n = -3, imax = 63.875a) iout (a) = hex2dec(8c hex data-e800) * 0.125a when iout pin voltage = 2.5v at 63.875a load.
isl68201 fn8696 rev.4.00 page 26 of 32 oct 17, 2017 r4 modulator the r4 modulator is an evolutiona ry step in r3 technology. like r3, the r4 modulator is a line ar control loop and variable frequency control during load transients to eliminate beat frequency oscillation at the switching frequency and maintains the benefits of current-mode hyst eretic controllers. in addition, the r4 modulator reduces regulator output impedance and uses accurate referencing to eliminate the need for a high-gain voltage amplifier in the compensation loop. the result is a topology that can be tuned to voltage-mode hysteretic transient speed while maintaining a linear control model and removes the need for any compensation. this greatly simplifies the regulator design for customers and reduces external component cost. stability the removal of compensation derives from the r4 modulator?s lack of need for high dc gain. in traditional architectures, high dc gain is achieved with an integrator in the voltage loop. the integrator introduces a pole in th e open-loop transfer function at low frequencies. that, combined with the double-pole from the output l/c filter, creates a three pole system that must be compensated to maintain stability. classic control theory requires a single-pole tran sition through unity gain to ensure a stable sy stem. current-mode architectures (includes peak, peak-valley, current-mode hysteric, r3, and r4) generate a zero at or near the l/c resonant point, effectively canceling one of the system?s po les. the system still contains two poles, one of which must be canceled with a zero before unity gain crossover to achieve stability. 8dh[15:0] r two read_temp vr temperature temp (c) = 1/{ln[rup*hex2dec(8d hex data)/(511 - hex2dec(8d hex data)/rntc(at +25c)]/beta + 1/298.15} -273.15 98h[7:0] r one 02h pmbus_revision in dicates pmbus revision 1.2 ad[15:0] block r two 8201h ic_device_id isl68201 device id ae[15:0] block r two 0003h ic_device_re vision isl68201 device revision d0[0:0] r/w one prog2[7:7] enable_pfm pfm operation 0h = pfm enabled (dcm at light load) 1h = pfm disabled (always ccm mode) d1[1:0] r/w one prog2[6:5] temp_comp thermal compensation: 0h = 30c; 01h = 15c; 02h = 5c; 03h = off d2[0:0] r/w one prog3[7:7] enable_ul trasonic ultrasonic pfm enable 0h = 25khz clamp disabled 1h = 25khz clamp enabled d3[0:0] r/w one prog3[6:6] ocp_behavior set latch or infinite retry for ocp fault: 0h = retry every 9ms; 01 = latch-off d4[2:0] r/w one prog3[2:0] av_gain r4 av gain (prog4, av gain multiplier = 2x) 0h = 84; 1h = 73; 2h = 61; 3h = 49 4h = 38; 5h = 26; 6h = 14; 7h = 2 r4 av gain (prog4, av gain multiplier = 1x) 0h = 42; 1h = 36.5; 2h = 30.5; 3h = 29.5 4h = 19; 5h = 13; 6h = 7; 7h = 1 d5{2:0] r/w one prog4[7:5] ramp_rate soft-start and margining dvid rate (mv/s) 0h = 1.25; 1h = 2.5; 2h = 5; 3h = 10; 4h = 0.078; 5h = 0.157 6h = 0.315; 7h = 0.625; d6[1:0] r/w one prog4[4:3] set_rr set rr 0h = 200k; 01h = 400k; 02h = 600k; 03h = 800k dc[7:0] r one read_prog1 read prog1 dd{7:0] r one read_prog2 read prog2 de[7:0] r one read_prog3 read prog3 df[7:0] r one read_prog4 read prog4 note: serial bus communication is valid 5.5m (typically, worst 6.5ms) after v cc , v in , 7vldo, and pvcc above por. the telemetry update rate is 108s. table 11. smbus, pmbus, and i 2 c supported commands (continued) command code access word length (byte) default value command name description
isl68201 fn8696 rev.4.00 page 27 of 32 oct 17, 2017 figure 25 illustrates the classic integrator configuration for a voltage loop error amplifier. while the integrator provides the high dc gain required for accurate regulation in traditional technologies, it also introduces a low-frequency pole into the control loop. figure 26 shows the open-loop response that results from the addition of an integrat ing capacitor in the voltage loop. the compensation components found in figure 25 are necessary to achieve stability. because r4 does not require a high-gain voltage loop, the integrator can be removed, reducing the number of inherent poles in the loop to two. the current-mode zero continues to cancel one of the poles, ensuri ng a single-pole crossover for a wide range of output filter choice s. the result is a stable system with no need for compensation components or complex equations to properly tune the stability. figure 27 shows the r4 error-amplifier that does not require an integrator for high dc gain to achieve accurate regulation. the result to the open loop response can be seen in figure 28 . transient response in addition to requiring a compen sation zero, the integrator in traditional architecture s also slows system re sponse to transient conditions. the change in comp voltage is slow in response to a rapid change in output voltage. if the integrating capacitor is removed, comp moves as quickly as v out , and the modulator immediately increases or decr eases switching frequency to recover the output voltage. the dotted red and blue lines in figure 29 represent the time delayed behavior of v out and v comp in response to a load transient when an integrator is used. the solid red and blue lines illustrate the increased response of r4 in the absence of the integrator capacitor. to optimize transient response and improve phase margin for very wide range applications, th e isl68201 integrates selectable av and rr options that move the dc gain and z1 point, as shown in figure 28 . however, the defaulted av gain of 42 and rr of 200k can cover many cases and provides sufficient gain and phase margin. for some extreme cases, lower av gain and bigger rr values are needed to provide a better phase margin and improve transient ringback. the optimal choice av and rr can be obtained, by simple monito ring transient response when adjusting av and rr values through the serial bus. figure 25. classical integrator error-amplifier configuration v comp compensation to counter integrator pole v out v dac v comp integrator for high dc gain integrator pole v out v dac figure 26. uncompensated integrator open-loop response f (hz) p1 p2 p3 l/c double-pole integrator pole z1 zero - 6 0 d b / d e c -20db /d e c -20db crossover required for stability compensator to add z2 is needed - 4 0 d b / d e c r3 loop gain (db) current-mode figure 27. non-integrated r4 error-amplifier configuration v out v dac r 1 r 2 v comp - + figure 28. uncompensated r4 open-loop response f (hz) p1 p2 l/c double-pole z1 current-mode zero -20db/dec system has 2 poles and 1 zero no compensator is needed r4 loop gain (db) - 2 0db/ d ec - 4 0 d b / d e c figure 29. r3 vs r4 idealized transient response r3 i t v comp r4 t t i out t t t v out
isl68201 fn8696 rev.4.00 page 28 of 32 oct 17, 2017 general application design guide this design guide is intended to provide a high-level explanation of the steps necessary to design a single-phase buck converter. it is assumed that the reader is familia r with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. output filter design the output inductors and the outp ut capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. the ou tput filter also must provide the transient energy until the re gulator can respond. because it has a low bandwidth compared to the switching frequency, the output filter limits the system transient response. the output capacitor must supply or sink load current while the current in the output inductors increase s or decreases to meet the demand. in high-speed converters, the outp ut capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, ? i; the load current slew rate, di/dt; and the maximum allowable output voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, esr, and es l (equivalent series inductance). at the beginning of the load transient, the output capacitors supply all of the transient current. the output voltage will initially deviate by an amount approximat ed by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output vo ltage deviation is less than the allowable maximum. neglecting the contribution of inductor current and regulator response, the output voltage initially deviates by an amount, as shown in equation 15 : the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the outp ut voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current, a voltage develops across the bulk capacitor esr equal to i l(p-p) (esr). thus, after the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance, as shown in equation 16 . because the capacitors are supplying a decreasing portion of the load current while the regulator re covers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper li mit on inductance. equation 17 gives the upper limit on l for cases when the trailing edge of the current transient causes a greater output to voltage deviation than the leading edge. equation 18 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected based on the lower of the two results. in equations 17 and 18 , l is the per-channel inductance and c is the total output capacitance. input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper mosfets, which is related to duty cycle and the number of active phases. the input rms current can be calculated with equation 19 . use figure 30 on page 29 to determine the input capacitor rms current requirement given the duty cycle, maximum sustained output current (i o ), and the ratio of the per-phase peak-to-peak inductor current (i l(p-p) to i o ). select a bulk capacitor with a ripple current rating, which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors sh ould also be at least 1.25 times greater than the maximum input voltage. low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. the result of the high current slew rates produced by the upper mosfets turn on and off requires low esl ceramic capacitors, which should be placed as close as possible to each upper mosfet drain to minimize board parasitic impedances and maximize noise suppression. ? v ? i esr esl l out --------------- - v in ? + ? 1 c out ---------------- - ? i 8nf sw ?? -------------------------- - ? + ? (eq. 15) ? i v out 1d C ?? ? l out f sw ? -------------------------------------- - = l out esr v out v in v out C ?? ? f sw v in v p-p(max) ?? --------------------------------------------------------- ? ? (eq. 16) l out 2cv out ?? ? i ?? 2 -------------------------------- ? v max ? i esr ? ?? C ? (eq. 17) l out 1.25 c ? ? i ?? 2 -------------------- ? v max ? i esr ? ?? C v in v out C ?? ?? ? (eq. 18) i in rms ? dd 2 C ?? io 2 ? d 12 ------ ? i ?? 2 ? + = (eq. 19)
isl68201 fn8696 rev.4.00 page 29 of 32 oct 17, 2017 design and layout considerations to ensure a first pass design, the schematics design must be done right with correct pinout and net names, and the board must be carefully laid out. as a general rule, power layers should be close together, either on the top or bottom of the board, with the weak analog or logic signal layers on the opposite side of the board or internal layers. the ground-plane layer should be in between power layers and the signal layers to provide shielding, often the layer below the top and the layer above the bottom should be the ground layers. there are two sets of components in a dc/dc converter, the power components and the small signal components. the power components are the most critical because they switch large amounts of energy. the small si gnal components connect to sensitive nodes or supply critic al bypassing current and signal coupling. the power components should be placed first and these include mosfets, input and output capacitors, and the inductor. keeping the distance between the power train and the control ic short helps keep the gate drive traces short. these drive signals include the lgate, ugate, gnd, phase, and boot. when placing mosfets, keep the source of the upper mosfets and the drain of the lower mosfets as close as thermally possible. input high-frequency capacitors should be placed close to the drain of the upper mosfets and the source of the lower mosfets. place the output inductor and output capacitors between the mosfets and the load. high frequency output decoupling capacitors (ceramic) should be placed as close as possible to the decoupling target, making use of the shortest connection paths to any internal planes. place the components in such a way that the area under the ic has less noise traces with high dv/dt and di/dt, such as ga te signals, phase node signals, and vin plane. tables 12 and 13 provide a design and layout checklist that the designer can reference. figure 30. normalized input-capacitor rms current vs duty cycle for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v out /v in ) input-capacitor current (i rms/ i o ) 0.6 0.2 0 0.4 i l(p-p) = 0.75 i o i l(p-p) = 0 i l(p-p) = 0.5 i o ? and 3.5k . decoupling (~ 0.1f/x7r) on the output end (not the pin) is optional and might be required for long sense trace and a poor layout (see figures 9 and 10 ). csen yes connect to the phase node side of the output inductor or current sensing resistor pin with l/dcr or esl/r sen matching network in close proximity to csen and csrtn pins. differentially routing back to the controller with at least 20 mils spacing from other traces. should not cross or go above/under the switching nodes [boot, phase, ugate, lgate], and power planes (vin, phase, vout) even though they are not in the same layer.
isl68201 fn8696 rev.4.00 page 30 of 32 oct 17, 2017 voltage regulator design materials to support vr design and layout, intersil also developed a set of tools and evaluation boards, as listed in table 14 and ordering information on page 5 . contact intersil?s local office or field support at www.intersil.com/ask for the latest available information. ntc yes place ntc 10k (murata, ncp15xh103j03rc, ? = 3380) in close proximity to the output inductor?s output rail, not close to mosfet side (see figure 19 ); the return trace should be 20 mils away from other traces. place 1.54k pull-up and decoupling capacitor (typically 0.1f) in close proximity to the controller. the pull-up resistor should be exactly tied to the same point as vcc pin, not through an rc filter. if not used, connect this pin to vcc. iout yes scale r so that the iout pin voltage is 2.5v at 63.875a load. place r and c in general proximity to the controller. the time constant of rc should be sufficient as an averaging function (>200s) for the digital iout. an external pull-up resistor to vcc placeholder is recommended to cancel i out offset at 0a load. see ? i out calibration ? on page 19 prog1-4 no the resistor divider must be referenced to vcc pin and the system ground (gnd); they can be placed anywhere. do not use decoupling capacitors on these pins. gnd yes directly connect to a low noise area of the system ground. the gnd pad should use at least four vias. separate analog ground and power ground with a 0 resistor is highly not recommended. fccm no do not place it across or under external components of the controller. keep it at least 20 mils away from sensitive nodes. pwm no do not place it across or under external components of the controller. keep it at least 20 mils away from any other traces. lgin no keep it at least 20 mils away from sensitive nodes. a series 100 resistor to low-side gate signal is required for noise attenuation. pvcc yes place x7r 4.7f in proximity to the pvcc pin and the system ground plane. table 12. design and layout checklist (continued) pin name noise sensitivity description table 13. top layout tips number description 1 the layer next to controller (top or bottom) should be a ground layer. separate analog ground and power ground with a 0 resistor is highly not reco mmended. directly connect gnd pad to low noise area of the syst em ground with at least four vias. 2 never place controller and its external components above or under vin plane or any switching nodes. 3 never share csrtn and vsen on the same trace. 4 place the input rail decoupling ceramic capacitors closely to the high-side fet on the same layer as possible. never use only one via and a trace connect the input rail decoupling ceramics capacitors; must co nnect to vin and gnd planes. 5 place all decoupling capacitors in close proximity to the controller and the system ground plane. 6 connect remote sense (vsen and rgnd) to the load and ceramic decoupling capacitors nodes; never run this pair above or below switching noise plane. 7 always double check critical component pinout and their respective footprints. table 14. available design assistance materials item description 1 smbus/pmbus/i 2 c communication tool with the powernavigator gui. 2 evaluation board schematics in orcad format and layout in allegro format. see ordering information on page 5 for details.
fn8696 rev.4.00 page 31 of 32 oct 17, 2017 isl68201 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2016-2017. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. for the most updated datasheet, application notes, related docume ntation, and related parts, please see the respective product information page found at www.intersil.com . for a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary . you can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please visit our website to make sure you have the latest revision. date revision change oct 17, 2017 fn8696.4 updated pin 11 and 12 descriptions on page 6. sep 25, 2017 fn8696.3 updated lgin pin description. updated figure 4, changed ?10.2v/9.24v? to ?10.08v/9.12v?. updated 3fh r up value in table 3. replaced entire paragraph on page 11. added units to r = 348 on page 17 above figure 11. on page 28 last sentence in paragraph in left column changed ?i c(p-p) ? to ?i l(p-p) ?. aug 29, 2017 fn8696.2 for figures 1 and 2 on page 3, added a resistor to the csrtn circuit. on page 1, updated the related literature section to current standards. added three demonstration boards to the ordering information table on page 5. removed table 15 on page 30 because the demonstratio n board information is in the ordering information section. mar 7, 2016 fn8696.1 removed unreleased parts from table 1. mar 2, 2016 fn8696.0 initial release
isl68201 fn8696 rev.4.00 page 32 of 32 oct 17, 2017 package outline drawing l24.4x4c 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified , tolerance: decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metalliz ed terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: for the most recent package outline drawing, see l24.4x4c .

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